Rambus Inc., a silicon IP and chip provider, announced Monday a broad portfolio of high-speed memory and SerDes PHYs for next-generation applications on TSMC’s N7 process technology.
Leveraging high-speed interface design expertise and using process technology, Rambus offers GDDR6, HBM2 and 112G LR PHY IP available for licensing. These solutions enable demanding applications for data center, networking, wireless 5G, HPC, ADAS, AI and ML.
As the fastest discrete memory interface from Rambus, GDDR6 memory PHY adds to TSMC’s most comprehensive portfolio of silicon-proven intellectual property (IP), design tools and Reference Flows through the TSMC IP Alliance Program, a key component of TSMC Open Innovation Platform (OIP). Along with HBM2 and 112G LR SerDes PHY, Rambus offers memory and serial link interfaces for a variety of high-performance applications.
The TSMC OIP initiative is a comprehensive design technology infrastructure that encompasses all critical IC implementation areas to reduce design barriers and improve first-time silicon success. OIP promotes the speedy implementation of innovation amongst the semiconductor design community and its ecosystem partners using TSMC’s IP, design implementation and design for manufacturability (DFM) capabilities, process technology and backend services.
Crucial to OIP are ecosystem interfaces and collaborative components initiated and supported by TSMC that empowers innovation throughout the supply chain and, in turn, drives creation and sharing of new revenue and profits. TSMC’s active accuracy assurance (AAA) initiative is key to OIP, providing the accuracy and quality required by the ecosystem interfaces and collaborative components.
TSMC’s Open Innovation model brings together creative thinking of customers and partners under the common goal of shortening each of the following: design time, time-to-volume, time-to-market and, ultimately, time-to-revenue.
The model features the foundry segment’s earliest and most comprehensive electronic design automation certification program, delivering timely design tool enhancement required by new process technologies; the foundry segment’s largest, most comprehensive and robust silicon-proven IP (intellectual properties) and library portfolio; and
comprehensive design ecosystem alliance programs covering EDA, library, IPs, and design service partners.
Expanding beyond the traditional GPU and graphics applications, GDDR6 and HBM2 address market needs in multiple, advanced applications like AI/ML, ADAS and networking, as memory bandwidth becomes more critical for overall system performance. As the industry rapidly transitions to 400 and 800GbE communications systems, 112G LR is a key building block necessary to support growing demand for more bandwidth in data center and network applications.
“TSMC OIP Alliance partners continue to deliver innovative solutions that will address the tremendous demands for computing power driven by AI and next-generation networks,” said Suk Lee, TSMC senior director, Design Infrastructure Management Division. “We’re pleased with the availability of Rambus’ high-speed memory and SerDes interface solutions on TSMC’s industry-leading N7 process technology to address customer’s requirements for the most demanding applications.”
“This announcement highlights Rambus’ leadership in high-speed SerDes and memory PHY IP, leveraging the company’s long tradition of signal- and power-integrity expertise,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “We are very proud to be able to offer these advanced solutions as part of the TSMC ecosystem.”
The Rambus GDDR6 and HBM2 Memory PHYs, and 112G LR SerDes PHY are currently available for licensing and integrating into system-on-chip (SoC) designs.
