Rambus validates interoperability of DDR4 memory IP offering for ARM-based data center systems


Rambus Inc. announced on Thursday validated interoperability of the Rambus DDR4 PHY and the ARM CoreLink DMC-620 Dynamic Memory Controller. Together, these IP blocks offer speeds of up to 3200 Mbps, the highest performance memory speed available on the market. This partnership provides a verified solution to chip designers, reducing design time and improving time-to-market for demanding data center and communications applications.

The CoreLink DMC-620 Dynamic Memory Controller is a fast, single-port Coherent Hub Interface (CHI) for transferring data from its CoreLink CMN-600 (Coherent Mesh Network) to the Rambus DDR4 memory PHY. CoreLink DMC-620 offers a combination of benefits to power, cost, and performance and guarantees interoperability with the Rambus DDR4 PHY, proven at speeds up to 3200 Mbps.

“Design teams face complex challenges in scaling the number of computing cores for advanced datacenter SoCs, while minimizing integration and testing time to ensure faster time-to-market,” said Jeff Defilippi, senior product manager, Infrastructure Business Unit, Arm. “Our collaboration with Rambus removes another degree of difficulty in designing purpose-built SoCs, resulting in higher-performing systems built for the most demanding cloud and enterprise workloads.”

The Rambus DDR4 memory PHY and CoreLink DMC-620 are both DFI 4.0 compliant, allowing the PHY and memory controller to interoperate. The Rambus memory PHY is fully JEDEC compliant to the DDR4 and DDR3/3L/3U standards.

The Rambus silicon-proven PHY combines performance and power efficiency with superior design flexibility to provide customers with a differentiated and easy to integrate solution.

Designed to meet the needs of the most demanding networking and data center applications, the silicon-proven PHY combines performance and power efficiency with superior design flexibility to provide customers with a differentiated and easy to integrate solution.

The PHY consists of a Command/Address (C/A) macro cell and Data (DQ) macro cells configured to create a 72 bits wide channel.

“With rising chip design and IP integration costs, these pre-validated solutions from Rambus and ARM provide customers with an easy path to implementation and the peace of mind of a proven solution,” said Hemant Dhulla, vice president of product of Rambus Memory and Interfaces Division. “Rambus strives to work with companies like Arm that are leaders in the IP ecosystem to deliver high-quality, comprehensive solutions to the market.”

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